Conventional semiconductor devices equipped with LSI (Large Scale Integration) integrated circuits are generally manufactured in a large quantity to have the same function based on function design, logic design, etc. These devices are suitable for mass production in that they can be produced efficiently at low cost, but they are unusable if functions are different, even slightly. For this reason, conventional semiconductor devices are not suitable for products having multiple varieties each produced in a small quantity, or products requiring frequent specification change or function change.
In light of the above, semiconductor devices that are programmable to allow the customer to set functions or change functions while in operation, have been developed.
One representative example of a programmable semiconductor device is a FPGA (Field Programmable Gate Array) having variable-function circuit cells, variable-signal lines, switch elements, and memory, wherein the aforementioned switches are turned on/off by transistors based on information in the memory to switch the variable-function circuit cells and variable-signal lines to achieve circuits for desired functions in a programmable manner.
However, conventional FPGAs use transistors to switch respective circuits and signal lines, and because the area occupied by each circuit or wiring is fixed, the degree of freedom is limited and their configuration may turn out to be very inefficient depending on the desired function circuit. Because of this, conventional FPGAs generally have poor efficiency per area of the layout, require LSIs of relatively large chip area, and consequently their cost performance is low. These FPGAs also present a problem of high manufacturing cost because their manufacturing process is long and complex due to the large number of wiring layers, etc. In addition, conventional FPGAs generate a problematic transmission delay due to parasitic capacitance and parasitic resistance if the wires connecting each circuit are positioned far away, leading to a possible malfunction in some cases. Or, to avoid this problem of transmission delay, many stages of buffers must be provided in the middle of signal lines, which lead to lower use efficiency of elements, increased chip area and other major problems as the number of long signal lines increases.
Refer to Patent Literature 1 and Patent Literature 2 for patent literatures relating to these FPGAs.
The aforementioned background has led to the development of early MPLD described below. This MPLD has the following configuration:
To be specific, this MPLD uses as the unit cell a MLUT which is equipped with a memory having the same number of address wires and data wires, and has a function that writes data needed to form desired functions to the memory and read, during logic operations, output data corresponding to these logic circuit operations from the memory based on address data corresponding to input signals, wherein a multiple number of the aforementioned MLUT unit cells are arranged side by side and wired with each other to serve as elements that provide functions equivalent to various circuits.
Here, MPLD stands for “Memory-based Programmable Logic Device,” while MLUT stands for “MPLD Look Up Table.” Refer to Patent Literature 3 and Non-patent Literature 1 for prior art literatures relating to MPLDs and MLUTs.
Background Art Literatures
Patent Literatures
    Patent Literature 1: Japanese Patent Laid-open No. 2000-36738    Patent Literature 2: Japanese Patent Laid-open No. 2002-164780    Patent Literature 3: WO 2007/060738 SpecificationNon-patent Literatures    Non-patent Literature 1: ITC-CSCC 2008 (The 23rd International Technical Conference on Circuits/Systems, Computers and Communications), pp. 557-560, “Low Cost PLD with High Speed Partial Reconfiguration,” Naoki Hirakawa, Masayuki Sato, Kazuya Tanigawa, and Tetsuo Hironaka.